1. Field of the Invention
The present invention relates to a method of forming a dielectric film and a structure thereof, and more particularly to a method of forming an interlayer dielectric film in a buried wiring structure and a structure thereof.
2. Description of the Background Art
Especially in a system LSI after the 0.18-micron generation, in order to achieve speed-up of devices, it is important to reduce signal delay of the devices. The signal delay of a device is a sum of signal delay in transistors and that in interconnection. As reduction in wiring pitch rapidly proceeds, the effect of the signal delay in interconnection becomes larger than that in transistors. Since the signal delay in interconnection is in proportion to the RC product (wiring resistance x wiring capacitance), in order to reduce the signal delay in interconnection, it is necessary to reduce the wiring resistance or the wiring capacitance. Therefore, an insulating film having lower relative dielectric constant than that of a silicon oxide film which is a general insulating film is used as an interlayer insulating film and a copper wiring having lower wiring resistance than that of an aluminum wiring which is a general metal wiring is used as a buried wiring, to reduce the signal delay in interconnection.
FIGS. 13 to 17 are cross sections showing a method of forming a buried copper wiring in the background art step by step. First, referring to FIG. 13, an underlying insulating film 102 made of silicon oxide film is formed on a silicon substrate 101. Though not shown in FIG. 13, semiconductor elements such as transistors are formed in the silicon substrate 101 and the underlying insulating film 102. For example, source/drain regions are selectively formed in an upper surface of the silicon substrate 101 and a gate electrode is selectively formed on the upper surface of the silicon substrate 101. Further, source/drain wirings connected to the source/drain regions are selectively formed in the underlying insulating film 102.
Subsequently, a first interlayer insulating film 103 is formed on the underlying insulating film 102. The first interlayer insulating film 103 is an insulating film made of a material having lower relative dielectric constant than that of the silicon oxide film. For example, a film such as Hydrogen Silsesquioxane, Methyl Silsesquioxane (MSQ), Poly arylether, Benzocyclobutene, Polytetrafluoroethylene, Xerogel or Aerogel is formed by the spin-on method. Alternatively, a film such as SiOF film, CF film, Parylene or SiOC film is formed by the CVD (Chemical Vapor Deposition) method. The relative dielectric constants of these materials range from about 1.8 to 3.7.
Subsequently, a second interlayer insulating film 104 is formed on the first interlayer insulating film 103. As the material of the second interlayer insulating film 104, a silicon nitride film (whose relative dielectric constant is 7.4), a silicon oxide film (whose relative dielectric constant ranges from 4.3 to 4.5), a silicon carbide film (whose relative dielectric constant ranges from 4,3 to 4.7) or the like is used.
Next, referring to FIG. 14, a photoresist 105 having a pattern with openings above regions in which the copper wirings are to be formed is formed on the second interlayer insulating film 104 by photolithography.
Next, referring to FIG. 15, using the photoresist 105 as an etching mask, the second interlayer insulating film 104 and the first interlayer insulating film 103 are etched in this order by anisotropic dry etching with high etching rate in a direction of depth of the silicon substrate 101, to expose an upper surface of the underlying insulating film 102. Through this step formed is a recess 106 having a bottom surface defined by the upper surface of the underlying insulating film 102 and a side surface defined by a sidewall of the first interlayer insulating film 103 and a sidewall of the second interlayer insulating film 104.
Next, referring to FIG. 16, the photoresist 105 is removed by ashing process using oxygen gas plasma 107. The ashing process is performed under a plasma forming condition that the RF power is 900 W, the chamber pressure is 133 Pa, the oxygen flow is 2000 sccm and the substrate temperature is 200° C.
Subsequently, a tantalum nitride (TaN) film (not shown) is entirely formed by sputtering method and then a copper film is so formed as to have such a film thickness as to fill the inside of the recess 106 by sputtering method or plating method. Next, referring to FIG. 17, the copper film and the TaN film are polished by the CMP (Chemical Mechanical Polishing) method until an upper surface of the second interlayer insulating film 104 is exposed. Through this step formed is a copper wiring 109 for filling the inside of the recess 106 with the not-shown TaN film interposed therebetween. Further, the TaN film is formed in order to prevent diffusion of copper atoms of the copper wiring 109 into the first and second interlayer insulating films 103 and 104.
Thus, in the background-art method of forming a buried copper wiring, the ashing process using the oxygen gas plasma 107 is performed under the plasma forming condition that the chamber pressure is 133 Pa and the substrate temperature is 200° C. in the step of removing the photoresist 105 (FIG. 16). For this reason, when an insulating film including Si—CnH2n+1 bond (n: natural number) therein, such as an MSQ film or an SiOC film including Si—CH3 bond, is used as the first interlayer insulating film 103, the Si—CH3 bond in the film is decomposed by the oxygen gas plasma 107 into Si—OH bond, as shown in the chemical equation (1):Si—CH3+2O2→Si—OH+CO2+H2O  (1)
As a result, as shown in FIG. 16, a damage layer 110 including a lot of Si—OH bond is formed inside the inner wall of the first interlayer insulating film 103. FIG. 18 is a graph showing an infrared absorption spectrum of an MSQ film with respect to the sidewall portion of the first interlayer insulating film 103 in a case where the MSQ film is adopted as the first interlayer insulating film 103. It can be seen from FIG. 18 that a spectrum caused by Si—OH bond, which does not exist before performing the ashing process (before irradiation of gas plasma), is generated after performing the ashing process (after irradiation of gas plasma).
Since the Si—OH bond has an orientational polarization component, the relative dielectric constant of the first interlayer insulating film 103 in which the damage layer 110 exists is higher than that of the first interlayer insulating film 103 in which no damage layer 110 exists. Further, since the Si—OH bond becomes an adsorption site of moisture in the atmosphere, a lot of absorbed moisture exists in the damage layer 110 and therefore the relative dielectric constant of the first interlayer insulating film 103 becomes still higher.
FIG. 19 is a graph showing variation in relative dielectric constant of the first interlayer insulating film 103 between before and after performing the ashing process for removing the photoresist 105. The relative dielectric constant after performing the ashing process (after irradiation of gas plasma) is higher than that before performing the ashing process (before irradiation of gas plasma) by 48%.
Thus, the background-art method of forming a buried copper wiring has the following problem: when the insulating film including Si—CnH2n+1 bond is adopted as the first interlayer insulating film 103, much of the Si—CnH2n+1 bond in the film is changed into Si—OH bond through the ashing process for removing the photoresist 105 and that causes a rise in relative dielectric constant of the first interlayer insulating film 103, leading to an increase in wiring capacitance.